Several types of electronic components are implemented with a circuit, which is integrated in a chip of semiconductor material. The chip is typically mounted on a carrier, so as to protect the chip from mechanical stresses, and is then encapsulated in a package. The chip carrier includes an insulating substrate with conductive tracks; each track is bonded to a corresponding terminal of the chip, and ends with a contact pad, typically for connection to a printed circuit board. Generally, chip carriers comprise several conductive layers wherein tracks transmitting signals and current are designed according to requirements depending upon both logical and electrical constraints as well as chip carrier manufacture constraints. Connections between layers are often done using vias or plated through holes.
Likewise, printed circuit board generally comprises several conductive layers formed in an insulating material, linked with vias or plated through holes, that are adapted to transmit signals between several electronic devices or between electronic devices and connectors.
When switching speeds of devices goes above 1 GHz clock rate, there is a need to no longer consider electrical signal transmission as a simple point to point transmission on a track but rather as the propagation of an electromagnetic wave supported by a current on a circuit trace. Such traces on electronic device carriers (chip carriers and printed circuit boards), also called transmission lines, represent a system comprising at least two conductive paths with specific properties (relation between transmission line width, distances between transmission lines, dielectric thickness between transmission lines and reference planes). These transmission lines comprise a conductive signal track or trace and another track and/or conductive plane, formed in close proximity and connected to a reference voltage or ground, for shielding the signal track from electromagnetic interference. The wave propagates along a transmission line defined by the signal track and an underlying reference voltage or ground plane, forming a complete loop path for the signal current. When the chip works at a high frequency, e.g. more than 1 GHz, the influence of the electronic device carrier may severely affects the performance of the electronic system as a whole.
Particularly, any discontinuity (or transition) in the transmission line, such as any change in structure, material properties and design features, represent a change in the electrical impedance of the media and this generates a reflected wave. Moreover, the system includes stray structures (capacitors, inductors and resistors), which act as low pass filters for the transmitted signal. As a consequence, the integrity of the electromagnetic wave propagated along the transmission line is not preserved.
The transmitted signal, switching between a low voltage (logic value 0) and a high voltage (logic value 1), generates a square-shaped wave. Due to all discontinuities in the transmission line, this wave undergoes degradation and is generally received as a pseudo-sinusoidal wave. The quality of the transmitted wave can be visualized by a so-called “eye diagram”, which plots the value of the received signal as a function of the phase of a clock signal controlling the electronic device. The above described discontinuities in the transmission line reduce the opening of the eye diagram; therefore, it is quite difficult to understand if a switching transition has actually taken place or if the shift of a signal baseline is due to a background noise.
These drawbacks are particular acute in modern electronic systems working with a reduced level of a power supply voltage (down to 1.2 V). In this case, there is a very low margin to discriminate between the logic value 0 (0V) and the logic value 1 (1.2V).
Moreover, the continuous trend towards miniaturization of electronic devices requires a reduction in the dimensions of chip carrier and printed circuit board conductive tracks. However, the impedance of the transmission line must be maintained at a desired value which optimizes the performance of the electronic device (typically 50Ω). Therefore, it is necessary to use a very thin dielectric layer between the conductive tracks and the ground plane (since the impedance is inversely proportional to the track width and directly proportional to the dielectric layer thickness). The short distance between the conductive tracks and the ground plane increases the value of a corresponding stray capacitance; as a consequence, the bandwidth of the transmission line is strongly reduced.
Therefore, as the quality of the transmission in the electronic device carrier, i.e. chip carrier or printed circuit board, is degraded it can cause the electronic device to operate at a frequency far lower than the working frequency which is afforded by the chip.
Such phenomena may be reduced by using stacked vias so as to minimize the number of transition as illustrated on FIG. 1. FIG. 1a shows a cross-section part of a chip carrier 100 of Ball Grid Array (BGA) type comprising a base or a core 105, three conductive layers 110a, 110b and 110c, a surface layer 115 and dielectric layers 120. Generally, dielectric layer are made of epoxy while conductive layer are made of copper however, other materials are also used. Electronic device carrier 100 further comprises two solder balls referred to as 125-1 and 125-2 for connections and a blind plated through hole 130. As illustrated, vias are used to connect conductive layers, e.g. tracks 135 and 140 are connected thanks to vias 145, 150 and 155. However, as shown with black arrows, the transmission line from track 135 to track 140 comprises five transitions that may not preserve integrity of the electromagnetic wave propagated along the transmission line as mentioned above. FIG. 1b shows a similar electronic device carrier 100′ wherein vias 145′, 150′ and 155′ are stacked so as to reduce the number of transitions along signal paths. Thus, the transmission line from track 135′ to track 140′ comprises only one transition as illustrated with black arrow.
Stacking of vias implies manufacturing implications that may be difficult to overcome with standard processes. Creating a buried via means to place a vertical connection between two different conductive layers with a dielectric placed between them. Processes to create this vertical connections are many such as mechanical drilling, laser and others. All of them start from one of conductive tracks present on one of the layers and need a receiving conductive pad in the other layer. Once the opening is achieved the receiving pad is exposed to a plating process that build the electrical conductive path along the aperture vertical walls establishing the continuity for an electrical signal between the two layers. The thickness of this metallization needs to be of a minimum value to compensate thermomechanical stresses and strains generated in the following manufacturing and operating conditions of the substrate. Plating of vias and blind vias conforms to vertical walls that have generally a reversed truncated cone shape. Dimensions of these vias are related to the technology used to create them, they usually have intrinsic plating limitations represented by the aspect ratio between the thickness of the dielectric to be drilled through over the selected diameter with the given drilling technology. The aspect ratio affects plating when the opening dimension, width over depth, reduces the flow of the plating solution within the via. Holes metallization operations in carrier manufacturing need to be accomplished in a reasonable time, with excellent uniformity along the vertical walls. Due to the extensive utilization of thin dielectric layers opening of the holes result larger than the depth of the holes. Plating of stacked vias requires to fill this large gap to achieve an acceptable receiving pad for the forthcoming stacked via extending the plating time. The longer time for plating is adversing the surface Copper circuitization conditions that results in an increased and higher thickness becoming no longer compatible with the fine pitch line to line requirements. Eventually a selective Copper etch-back operation is needed to re-thin the Copper on surface prior to etch the fine pitch circuitry. Manufacturing operations need to account for process tolerances that affect the minimum design dimensions of the stacked vias with further effect of their electrical impedance value.
U.S. Pat. No. 5,758,413 assigned to IBM Corporation disclosed a method of manufacturing a multiple layer circuit board with stacked vias of fine dimension and pitch. A base laminate with conductive pattern is coated with a dielectric which is photolithographically processed to create holes exposing selected regions of the underlying conductive pattern. The holes through the dielectric are plated to form via connections between the surface and the conductive pattern on the base laminate. The recess created by the via is filled with a conductive and plateable polymer which upon curing forms a conductive plug. A second dielectric layer is deposited on the board structure and in succession photolithographically processed to expose the underlying plated via and plug. The hole in the second dielectric-is plated and filled with conductive polymer so as to create a second via vertically aligned with and electrically connected to the underlying first via. The ability to form fine pitch stacked vias is particularly important for printed circuit board structures such as carriers of flip chip die, in that the fine pitch of the solder ball array of the flip chip needs to be expanded and/or disbursed through multiple board layers with minimum area and electrical degradation.
However, such kind of technology presents drawbacks for carrying high-speed signal in electronic device carriers, particularly in electronic device carriers dedicated to end customer telecommunication products. Firstly; it requires additional manufacturing steps that are not required in standard electronic device carrier manufacturing process and thus, increases their prices. Secondly, the transmission path along stacked vias is done through several conductive materials, e.g. copper and conductive polymer, that may disturb high-speed signals, e.g. generating signal reflection. Finally, the use of several conductive materials to stack vias induces mechanical and chemical constraints that may lead to unreliable electrical contacts between stacked vias and/or electronic device carrier fragility.